bosch_can_user guide 4/10 - 3. Programmer’s Model

3. Programmer’s Model

3.1 Hardware Reset Description

3.2 CAN Protocol Related Registers

3.2.1 CAN Control Register (addresses 0x01 & 0x00)

3.2.2 Status Register (addresses 0x03 & 0x02)

3.2.2.1 Status Interrupts

3.2.3 Error Counter (addresses 0x05 & 0x04)

3.2.4 Bit Timing Register (addresses 0x07 & 0x06)

3.2.5 Test Register (addresses 0x0B & 0x0A)

3.2.6 BRP Extension Register (addresses 0x0D & 0x0C)

3.3 Message Interface Register Sets

3.3 Message Interface Register Sets

3.3.2 IFx Command Mask Registers

3.3.2.1 Direction = Write

3.3.2.2 Direction = Read

3.3.3 IFx Message Buffer Registers

3.3.3.1 IFx Mask Registers

3.3.3.2 IFx Arbitration Registers

3.3.3.3 IFx Message Control Registers

3.3.3.4 IFx Data A and Data B Registers

3.3.4 Message Object in the Message Memory

3.4 Message Handler Registers

3.4.1 Interrupt Register (addresses 0x09 & 0x08)

3.4.2 Transmission Request Registers

3.4.3 New Data Registers

3.4.4 Interrupt Pending Registers

3.4.5 Message Valid 1 Register